A 5-bit 1-GS/s flash-ADC in 0.13-μm CMOS using active interpolation

被引：0

作者：

Viitala, Olli ^{[1
]}

Lindfors, Saska ^{[1
]}

Halonen, Kari ^{[1
]}

机构：

[1] Aalto Univ, Elect Circuit Design Lab, POB 3000, FIN-02015 Helsinki, Finland

来源：

ESSCIRC 2006: PROCEEDINGS OF THE 32ND EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2006年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This work presents a 5-bit 1-GS/s flash-ADC in 0.13-mu m CMOS technology. An active interpolation topology is used in the comparator inputs to reduce power consumption and input capacitance of the converter. Operating at 1.056-GS/s the ADC consumes 46 mW of power from a 1.2 V supply and provides an ENOB of 4.73 bits and an SFDR of 43.2 dBc at a signal frequency of 102 MHz. The ADC has an ERBW of 470 MHz and a FoM of 1.8 pJ/convstep. Area consumption for the converter is 0.2 mm(2).

引用

页码：412 / +

页数：2

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