NSP: Physical compact model for stacked-planar and vertical Gate-All-Around MOSFETs

被引：0

作者：

Rozeau, O. ^{[1
]}

Martinie, S. ^{[1
]}

Poiroux, T. ^{[1
]}

Triozon, F. ^{[1
]}

Barraud, S. ^{[1
]}

Lacord, J. ^{[1
]}

Niquet, Y. M. ^{[2
]}

Tabone, C. ^{[1
]}

Coquand, R. ^{[1
]}

Augendre, E. ^{[1
]}

Vinet, M. ^{[1
]}

Faynot, O. ^{[1
]}

Barbe, J. -Ch. ^{[1
]}

机构：

[1] CEA Leti, Minatec Campus, F-38054 Grenoble, France

[2] CEA, INAC, Grenoble, France

来源：

2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2016年

关键词：

INVERSION;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work, a predictive and physical compact model for NanoWire/NanoSheet (NW/NS) Gate-All-Around (GAA) MOSFET is presented. Based on a novel methodology for the calculation of the surface potential including quantum confinement, this model is able to handle arbitrary NW/NS cross-section shape of stacked planar and vertical GAA MOSFETs (circular, square, rectangular). This Nanowire Surface Potential (NSP) based model, validated both by numerical simulations and experimental data, is demonstrated to be very accurate in all operation regimes of GAA MOSFETs.

引用

页数：4

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