Micro-Architectural Power Estimation and Optimization

被引：0

作者：

Hidaji, Babak ^{[1
]}

Andalibizadeh, Mohamad Reza ^{[1
]}

Alipour, Salar ^{[1
]}

机构：

[1] Chalmers, Dept Comp Sci & Engn, S-41296 Gothenburg, Sweden

来源：

2009 IEEE INTERNATIONAL CONFERENCE ON ELECTRO/INFORMATION TECHNOLOGY | 2009年

关键词：

D O I：

暂无

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

Today power optimization is an important field of research due to the increasing need for less power consumption, dramatic decrease of circuit's MTBF on high temperature and cooling difficulties. It is investigated that only 30% improvement in battery performance will be obtained in five years [1]. This paper is an overview on Power estimation and optimization researches and the overall flow of presenting the information is based on the reference [17]. We review the architectural template and the methods to provide model for power consumption of different types of components. Some common optimization techniques including clock-gating, exploiting the common case of the design and managing voltage are being reviewed.

引用

页码：444 / 448

页数：5

共 16 条

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