Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks

被引：69

作者：

Kamali, Hadi Mardani ^{[1
]}

Azar, Kimia Zamiri ^{[1
]}

Homayoun, Houman ^{[1
]}

Sasan, Avesta ^{[1
]}

机构：

[1] George Mason Univ, Farifax, VA 22030 USA

来源：

PROCEEDINGS OF THE 2019 56TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC) | 2019年

关键词：

Reverse Engineering; Logic Locking; SAT Attack; Logarithmic Network;

D O I：

10.1145/3316781.3317831

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

In this paper, we propose a novel and SAT-resistant logic-locking technique, denoted as Full-Lock, to obfuscate and protect the hardware against threats including IP-piracy and reverse-engineering. The Full-Lock is constructed using a set of small-size fully Programmable Logic and Routing block (PLR) networks. The PLRs are SAT-hard instances with reasonable power, performance and area overheads which are used to obfuscate (1) the routing of a group of selected wires and (2) the logic of the gates leading and proceeding the selected wires. The Full-Lock resists removal attacks and breaks a SAT attack by significantly increasing the complexity of each SAT iteration.

引用

页数：6

共 32 条

[1]

Aloul FA, 2002, DES AUT CON, P731, DOI 10.1109/DAC.2002.1012719

[2]

[Anonymous], 1991, IJCAI, DOI DOI 10.5555/1631171.1631221

[3]

Azar K. Z., 2019, IACR Trans. Cryptogr. Hardw. Embed. Syst, P97, DOI DOI 10.46586/TCHES.V2019.I1.97-122

[4]

Azar K. Z., 2019, P GREAT LAK S VLSI G, P6

[5] LUT-Lock: A Novel LUT-based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection [J].

Kamali, Hadi Mardani ;

Azar, Kimia Zamiri ;

Gaj, Kris ;

Homayoun, Houman ;

Sasan, Avesta .

2018 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2018, :405-410

[6]

MITCHELL D, 1992, AAAI-92 PROCEEDINGS : TENTH NATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE, P459

[7] A comparative study of two Boolean formulations of FPGA detailed routing constraints [J].

Nam, GJ ;

Aloul, F ;

Sakallah, KA ;

Rutenbar, RA .

IEEE TRANSACTIONS ON COMPUTERS, 2004, 53 (06) :688-696

[8]

RAJENDRAN J., 2015, IEEE T COMPUT, V64, P2

[9]

Rajendran J, 2012, DES AUT CON, P83

[10] SRCLock: SAT-Resistant Cyclic Logic Locking for Protecting the Hardware [J].

Roshanisefat, Shervin ;

Kamali, Hadi Mardani ;

Sasan, Avesta .

PROCEEDINGS OF THE 2018 GREAT LAKES SYMPOSIUM ON VLSI (GLSVLSI'18), 2018, :153-158

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