A 160K gates/4.5 KBSRAM H.264 video decoder for HDTV applications

被引：46
作者：
Lin, Chien-Chang [1 ]
Chen, Jia-Wei
Chang, Hsiu-Cheng
Yang, Yao-Chang
Yang, Yi-Huan Ou
Tsai, Ming-Chih
Guo, Jiun-In
Wang, Jinn-Shyan
机构：
[1] Natl Chung Cheng Univ, Dept Comp Sci & Informat Engn, Chiayi 621, Taiwan
[2] Natl Chung Cheng Univ, Dept Elect Engn, Chiayi 621, Taiwan
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2007年 / 42卷 / 01期
关键词：
H264/AVC video decoder architecture design; low-cost design; low power consumption;
D O I：
10.1109/JSSC.2006.886537
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a low-cost H.264/AVC video decoder design is presented for high definition television (HDTV) applications. Through optimization from algorithmic and architectural perspectives, the proposed design can achieve real-time H.264 video decoding on HD1080 video (1920 x 1088@30 Hz) when operating at 120 MHz with 320 mW power dissipation. Fabricated by using the TSMC one-poly six-metal 0.18 mu m CMOS technology, the proposed design occupies 2.9 x 2.9 mm(2) silicon area with the hardware complexity of 160K gates and 4.5K bytes of local memory.
引用
收藏
页码：170 / 182
页数：13
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