Line Reduction in Reversible Circuits using KFDDs

Reversible computing has been theoretically shown to be an efficient approach over conventional computing. This is due to the property of virtually zero power dissipation in reversible circuits. A major concern in reversible circuits is the number of circuit lines which corresponds with qubits. Qubits are a limited resource. There are various reversible logic synthesis algorithms which require a significant number of additional constant lines. In this paper we explore the line reduction problem using a synthesis approach based on decision diagrams. We have added a sub-circuit for a positive Davio node structure to the existing node structures given in [1] with a shared node ordering in OKFDDs. OKFDDs are a combination of OBDDs and OFDDs, thus exhibiting the advantages of both. Our approach shows that the number of circuit lines and quantum cost can be reduced using OKFDDs with our new sub-circuit and shared node ordering.