Reconfigurable Radix-2kx3 Feedforward FFT Architectures

被引:0
作者
Tsai, Wei-Lun [1 ]
Chen, Sau-Gee [1 ]
Huang, Shen-Jui [2 ]
机构
[1] Natl Chiao Tung Univ, Inst Elect, Dept Elect Engn, Hsinchu, Taiwan
[2] Intelligo Corp, Hsinchu, Taiwan
来源
2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2019年
关键词
FFT; MDC; mixed-radix; non-power-of-two; HARDWARE ARCHITECTURE; DESIGN; PROCESSOR; IMPLEMENTATION;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Due to the increasing demand for high-throughput and low-cost mobile devices, design of high-parallel reconfigurable FFT processors has become more and more important. However, FFT lengths varied, designing a multi-length FFT processor with the requirement meet has become unprecedentedly challenging, especially as the FFT lengths includes non-power-of-two. In this paper, reconfigurable mixed-radix 2(k)x3-point feedforward FFT architectures are proposed. It can be realized as any power-of-two parallelism to achieve the sweet spot, with performs high enough to meet the requirement and still promise a reasonable cost. A proposed feedforward radix-3 FFT is applied in the architecture, empowering the FFT processor to achieve high parallelisms. An 8-parallel 1282048/1536-point FFT processor for the 4G LTE system is implemented with TSMC 90nm technology. Compared to the existing designs, this work offers a high-throughput and high area-efficiency solution for mixed-radix FFT operation.
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页数:5
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