Design and Analysis of a 12-b Current-Steering DAC in a 14-nm FinFET Technology for 2G/3G/4G Cellular Applications

被引：10

作者：

Kim, Jaekwon ^{[1
]}

Jang, Woojin ^{[2
]}

Lee, Yanghoon ^{[2
]}

Kim, Wan ^{[2
]}

Oh, Seunghyun ^{[2
]}

Lee, Jongwoo ^{[2
]}

Choi, Jaehyuk ^{[1
]}

Chun, Jung-Hoon ^{[1
]}

Byunghak, Thomas ^{[2
]}

机构：

[1] Sungkyunkwan Univ, Coll Informat & Commun Engn, Suwon 440746, South Korea

[2] Samsung Elect, S LSI Div, Hwasung 446711, South Korea

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2019年 / 66卷 / 10期

关键词：

Transmitter; level-shifter; digital-to-analog converter (DAC); barrel-shifter DEM; FinFET; BANDWIDTH; GHZ; DBC;

D O I：

10.1109/TCSI.2019.2913174

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 14-nm FinFET CMOS 12-b current-steering digital-to-analog converter (DAC) for 2G/3G/4G cellular applications is presented herein. Bit segmentations of a 6-bit thermometer and 6-bit binary coding are adopted, utilizing switching-order shuffling in combination with dynamic element matching (DEM) to suppress the spurious tones owing to the current-source mismatch in three-dimensional FinFETs. In addition, output switches are designed to achieve make-before-break operation with the proposed low crossing point level shifter. Moreover, an output full-scale current trimming method is applied to maximize the power efficiency of the envelope-tracking (ET). The active area of a single DAC is 0.036 mm(2), its power consumption is 6.1 mW, and its SFDR is 80 dBc.

引用

页码：3723 / 3732

页数：10

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