Implementation of high-speed SHA-1 architecture

被引：13
|
作者：
Lee, Eun-Hee [1 ]
Lee, Je-Hoon [1 ]
Park, Il-Hwan [2 ]
Cho, Kyoung-Rok [1 ]
机构：
[1] Chungbuk Natl Univ, Chungbuk Informat Tech Ctr BK21, Cheongju 361763, South Korea
[2] Natl Secur Res Inst, Taejon, South Korea
来源：
IEICE ELECTRONICS EXPRESS | 2009年 / 6卷 / 16期
基金：
新加坡国家研究基金会;
关键词：
cryptography; secure hash algorithm; hardware design;
D O I：
10.1587/elex.6.1174
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper proposes a new SHA-1 architecture to exploit higher parallelism and to shorten the critical path for Hash operations. It enhances a performance without significant area penalty. We implemented the proposed SHA-1 architecture on FPGA that showed the maximum clock frequency of 118 MHz allows a data throughput rate of 5.9 Gbps. The throughput is about 26% higher, compared to other counterparts. It supports cryptography of high-speed multimedia data.
引用
收藏
页码：1174 / 1179
页数：6
相关论文
共 50 条
  • [1] High-Speed FPGA Implementation of the SHA-1 Hash Function
    Lee, Je-Hoon
    Kim, Sang-Choon
    Song, Young-Jun
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2011, E94A (09) : 1873 - 1876
  • [2] High-speed FPGA implementation of the SHA-1 Hash function
    Kakarountas, A. P.
    Theodoridis, G.
    Laopoulos, T.
    Goutis, C. E.
    2005 IEEE INTELLIGENT DATA ACQUISITION AND ADVANCED COMPUTING SYSTEMS: TECHNOLOGY AND APPLICATIONS, 2005, : 211 - 215
  • [3] A High-Speed SHA-1 IP Core For 10 Gbps Ethernet Security Processor
    Liu, Yang
    Wu, Liji
    Niu, Yun
    Zhang, Xiangmin
    Gao, Zhigiang
    PROCEEDINGS OF THE 2012 EIGHTH INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND SECURITY (CIS 2012), 2012, : 237 - 241
  • [4] FPGA implementation of SHA-1 algorithm
    Dai, ZB
    Zhou, N
    2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 1321 - 1324
  • [5] Holistic Methodology for Designing Ultra High-Speed SHA-1 Hashing Cryptographic Module in Hardware
    Michail, H.
    Goutis, C.
    EDSSC: 2008 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, 2008, : 144 - 147
  • [6] VLSI Implementation of High-speed SHA-256
    Bai, Ling
    Li, Shuguo
    2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2009, : 131 - +
  • [7] High Speed Implementation of the Keyed-Hash Message Authentication Code (HMAC) Based on SHA-1 Algorithm
    Suhaili, Shamsiah Binti
    Watanabe, Takahiro
    ADVANCED SCIENCE LETTERS, 2017, 23 (11) : 11096 - 11100
  • [8] A Flexible Hardware Implementation of SHA-1 and SHA-2 Hash Functions
    Docherty, James
    Koelmans, Albert
    2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 1932 - 1935
  • [9] Hardware architecture and cost estimates for breaking SHA-1
    Satoh, A
    INFORMATION SECURITY, PROCEEDINGS, 2005, 3650 : 259 - 273
  • [10] An efficient implementation of SHA-1 I hash function
    Wang, Guoping
    2006 IEEE INTERNATIONAL CONFERENCE ON ELECTRO/INFORMATION TECHNOLOGY, 2006, : 575 - 579
12345