While the cost of silicon drops over years, the IC test cost basically stays flat. Hence, the percentage of the test cost in the overall chip cost increases significantly. For the total test cost, the RF test cost is a major contributor due to its tester requirement as well as the complexity of the RF parametric and functional tests. Design for Test (DFT) is a natural step to take to reduce the overall testing cost when the cost of the silicon to implement many Built-In Self Test (BIST) is virtually negligible. This article presents general guidelines for the RF IC, especially for the System on Chip (SoC) and System in Package (SiP) parts. It discusses the specific guidelines for DFT in order to reduce the RF test cost while still keeping acceptable test quality for both RF parameters and functionalities.
