A high-speed, low-power bipolar digital circuit for Gb/s LSI's: Current mirror control logic

被引：15

作者：

Kishine, K

Kobayashi, Y

Ichino, H

机构：

[1] NTT System Electronics Laboratories, Atsugi-shi

[2] NTT Electronics Technology, Atsugi-shi

[3] Kyoto University, Kyoto

[4] Elec. Communication Laboratories, Nippon Telegraph and Tel. Corp., Tokyo

[5] NTT System Electronics Laboratories, Kanagawa

[6] Tokyo Institute of Technology, Tokyo

[7] NTT Elec. Commun. Laboratories, Nippon Telegraph and Tel. Corp., Kanagawa

[8] Process Technology Division, NTT Elec. Technology Corporation, Kanagawa

[9] Osaka University, Osaka

[10] High-Speed Intgd. Circt. Laboratory, NTT System Electronics Laboratories, Kanagawa

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1997年 / 32卷 / 02期

关键词：

bipolar; CMCL; current mirror; digital; highspeed; low-power; low-voltage;

D O I：

10.1109/4.551913

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel low-power bipolar circuit for Gb/s LSI's, current mirror control logic (CMCL), is described, To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits, This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL, This CMCL circuit achieves 3.1-Gb/s (D-FF) and 43-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF).

引用

页码：215 / 221

页数：7

共 14 条

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