Techniques for minimizing the basal plane dislocation density in SiC epilayers to reduce Vf drift in SiC bipolar power devices

Forward voltage instability, or V-f drift, has confounded high voltage SiC device makers for the last several years. The SiC community has recognized that the root cause of V-f drift in bipolar SiC devices is the expansion of basal plane dislocations (BPDs) into Shockley Stacking Faults (SFs) within device regions that experience conductivity modulation. In this presentation, we detail relatively simple procedures that reduce the density of V-f drift inducing BPDs in epilayers to < 10 cm(-2) and permit the fabrication of bipolar SiC devices with very good V-f stability. The first low BPD technique employs a selective etch of the substrate prior to epilayer growth to create a near on-axis surface where BPDs intersect the substrate surface. The second low BPD technique employs lithographic and dry etch patterning of the substrate prior to epilayer growth. Both processes impede the propagation of BPDs into epilayers by preferentially converting BPDs into threading edge dislocations (TEDs) during the initial stages of epilayer growth. With these techniques, we routinely achieve V-f stability yields of up to 90% in devices with active areas from 0.006 to 1 cm(2), implying that the utility of the processes is not limited by device size.