A built-in redundancy-analysis scheme for self-repairable RAMs with two-level redundancy

被引:8
|
作者
Huang, Yu-Jen [1 ]
Chang, Da-Ming [1 ]
Li, Jin-Fu [1 ]
机构
[1] Natl Cent Univ, Dept Elect Engn, Adv Reliable Syst Lab, Chungli 320, Taiwan
来源
21ST IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS | 2006年
关键词
D O I
10.1109/DFT.2006.6
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
With the increasing demand of memories in system-on-chip (SOC) designs, developing efficient yield-improvement techniques for memories becomes an important is-sue. Built-in self-repair (BISR) technique has become a popular method for repairing defective embedded memories. To allocate redundancy efficiently, built-in redundancy-analysis (BIRA)function is usually needed for designing a BISR scheme. This paper presents an efficient BIRA scheme for RAMs with two-level redundancy (i.e., spare rows, spare columns, and spare words). Experimental results show that the repair rate of the proposed BIRA scheme approximates to that of the exhaustive search with the same redundancy organization. Furthermore, the repair rate of the proposed BIRA scheme with two-level redundancy is higher than that of the exhaustive search scheme with one-level redundancy (i.e., spare rows and spare columns). The area cost of the proposed BIRA scheme is low. For example, the hardware overhead of the proposed BIRA scheme for an 8Kx64-bit RAM with three spare rows, three spare columns, and two spare words is only about 2%.
引用
收藏
页码:362 / +
页数:2
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