Design and implementation of image kernels using reversible logic gates

被引:4
|
作者
Raveendran, Sithara [1 ,2 ]
Edavoor, Pranose Jose [1 ,2 ]
Yernad Balachandra, Nithin Kumar [1 ,2 ]
Moodabettu Harishchandra, Vasantha [1 ,2 ]
机构
[1] Natl Inst Technol Goa, Dept Elect & Commun Engn, Farmagudi 403401, Goa, India
[2] Natl Inst Technol Goa, Dept Elect & Elect Engn, Farmagudi 403401, Goa, India
关键词
logic gates; field programmable gate arrays; image enhancement; edge detection; logic design; image kernels; reversible logic gates; filtering enhancing; reversible logic literature; filter kernel; reversible logic based design; ancilla inputs; gate count; 512$512x512 standard images; filtered images;
D O I
10.1049/iet-ipr.2019.1681
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
This study presents the implementation of image kernels used for filtering and enhancing the images using reversible logic gates, a first in reversible logic literature. Image enhancement/filtering is achieved by performing convolution of an image with a filter kernel. This work proposes reversible logic based design and implementation of six filter kernels. The filter kernels implemented are Gaussian blur, Laplacian outline, Sobel, Emboss, Sharpen and Prewitt edge detection. The kernels are implemented individually using reversible logic gates and the designs are measured in terms of quantum cost, garbage outputs, ancilla inputs and gate count. The functional verification is carried out using 512x512 standard images on Kintex 7 FPGA platform. The filtered images from the proposed design have an average structural similarity index of 0.92.
引用
收藏
页码:4110 / 4121
页数:12
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