Alpha-induced multiple cell upsets in standard and radiation hardened SRAMs manufactured in a 65 nm CMOS technology

被引:40
作者
Gasiot, G. [1 ]
Giot, D. [1 ]
Roche, P. [1 ]
机构
[1] STMicroelect, Cent CAD & Design Solut, Front End Technol & Mfg, F-38926 Crolles, France
关键词
alpha experiments; CMOS; 65; nm; full 3-D device simulation; multiple cell upset; robust SRAM; soft error rate;
D O I
10.1109/TNS.2006.885007
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Accelerated alpha-Soft Error Rate (SER) measurements are carried out on regular and radiation-hardened SRAMs in a 65 run CMOS technology. Results are first compared to previous experimental radiation data in 130 nm and 90 run. Second, the SER increase measured-in 65 nm is investigated through (i) Multiple Cell Upsets (MCU) counting and classification from experimental bitmap errors and (ii) full 3-D device simulations on SRAM bitcells to assess the PMOS-off sensitivity and the NMOS SEU threshold LET (LETth) of each tested technologies. Finally, process changes are also scanned to shed light on the 65 nm SRAM response to alpha particles.
引用
收藏
页码:3479 / 3486
页数:8
相关论文
共 25 条
  • [1] [Anonymous], 89 JEDEC JESD
  • [2] BAUMANN R, 2002, P INT EL DEV M
  • [3] Radiation-induced soft errors in advanced semiconductor technologies
    Baumann, RC
    [J]. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2005, 5 (03) : 305 - 316
  • [4] SRAM SER in 90,130 and 180 nm bulk and SOI technologies
    Cannon, EH
    Reinhardt, DD
    Gordon, MS
    Makowenskyj, PS
    [J]. 2004 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS, 2004, : 300 - 304
  • [5] Various SEU conditions in SRAM studied by 3-D device simulation
    Castellani-Coulié, K
    Palau, JM
    Hubert, G
    Calvet, MC
    Dodd, PE
    Sexton, F
    [J]. IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2001, 48 (06) : 1931 - 1936
  • [6] DAI C, 1999, P S VLSI TECHN
  • [7] Fukui H, 2005, 2005 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P222
  • [8] GIOT D, 2006, IN PRESS RADECS 06
  • [9] HARELAND S, 2001, P S VLSI
  • [10] Hazucha P., 2003, P IEEE INT EL DEV M