Development of Bumpless Stacking With Bottom-Up TSV Fabrication

被引：7

作者：

Lee, Shih-Wei ^{[1
]}

Chen, Kuan-Neng ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 30050, Taiwan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2017年 / 64卷 / 04期

关键词：

3-D integration (3-D-I); bumpless stacking; through-silicon via (TSV); INTEGRATED-CIRCUITS; INTERCONNECT; TECHNOLOGY; SILICON;

D O I：

10.1109/TED.2017.2657324

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 3-D integration technology using bump less stacking based on a new bottom up Cu electroplating method without backside Cu chemical-mechanical planarization removal is presented in this paper. The approach successfully achieves via plating without thick Cu overburden by probing unique bottom electrodes for different I/O ports of TSV without additional steps in the conventional processes. The concepts and fabrication processes are described in detail. The results obtained from through silicon via (TSV) daisy chains show excellent electrical characteristics and good reliability in leakage current measurement. The proposed approach therefore has potential for low-cost via-last 3-D integration.

引用

页码：1660 / 1665

页数：6

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