A Piecewise Linear 10 Bit DAC Architecture With Drain Current Modulation for Compact LCD Driver ICs

被引：32

作者：

Jeon, Yong-Joon ^{[1
]}

Lee, Hyung-Min ^{[2
]}

Lee, Sung-Woo ^{[2
]}

Cho, Gyu-Hyeong ^{[2
]}

Kim, Hyoung Rae ^{[3
]}

Choi, Yoon-Kyung ^{[3
]}

Lee, Myunghee ^{[3
]}

机构：

[1] Korea Adv Inst Sci & Technol, Dept Elect Engn & Comp Sci, C&S Lab, Taejon 305701, South Korea

[2] Korea Adv Inst Sci & Technol, Sch Elect Engn & Comp Sci, Div Elect Engn, Taejon 305701, South Korea

[3] Samsung Elect, Yongin, South Korea

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2009年 / 44卷 / 12期

关键词：

Cascaded-dividing DAC; data driver; drain current modulation; interpolation; LCD; piecewise linear;

D O I：

10.1109/JSSC.2009.2035547

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A piecewise linear 10 bit DAC for LCD data driver with robust interpolation method of drain current modulation is presented. It has higher effective bit resolution than the linear 10 bit switched-capacitor DAC when applied to nonlinear liquid crystal characteristics. By adopting a simultaneous design flow based on the estimations for the mismatch and nonlinearity effects on channel driver performance, the proposed DAC accomplishes good DNL of 0.37 LSB and excellent channel uniformity such that the mean and the standard deviation of the maximum output voltage deviations are 6.35 mV and 0.54 mV, respectively. The data driver with the new interpolation shows 8.2% shrinkage of chip area in comparison with the conventional 8 bit data driver with R-DAC.

引用

页码：3659 / 3675

页数：17

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