A large-scale Reconfigurable Analog Signal Processor (RASP) IC

被引:23
作者
Twigg, Christopher M. [1 ]
Hasler, Paul [1 ]
机构
[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA
来源
PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2006年
关键词
D O I
10.1109/CICC.2006.320937
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The Reconfigurable Analog Signal Processor (RASP), one of the first Large-Scale Field-Programmable Analog Arrays (FPAAs), is composed of 56 Computational Analog Blocks (CABs). Each CAB contains various levels of analog computational granularity utilizing over 50,000 programmable analog elements. Bias currents are programmable to within 0.2% from 100 pA to greater than 3 pA. Internal bandwidths are greater than 50 MHz, and the kT/C noise can be adjusted using the drawn capacitances and routing network parasitics. A range of compiled circuits and resulting signal processing systems are presented.
引用
收藏
页码:5 / 8
页数:4
相关论文
共 12 条
  • [1] *AN, 2003, AN FPAA FAM OV
  • [2] BASKAYA F, 2005, INT C FIELD PROGR LO, P421
  • [3] CHAWLA R, 2004, CUST INT CIRC C ORL
  • [4] A VLSI analog computer/digital computer accelerator
    Cowan, GER
    Melville, RC
    Tsividis, YP
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (01) : 42 - 53
  • [5] *FAST AN SOL LTD, 1999, TOT REC AN CIRC TRAC
  • [6] GRAHAM D, 2004, P INT S CIRC SYST M
  • [7] HALL TS, 2005, INT J EMBEDDED SYSTE
  • [8] HALL TS, 2005, T CIRCUITS SYSTEMS, V1
  • [9] LEE KFE, 1995, ISSCC FEB, P198
  • [10] A current-mode based field programmable analog array architecture for signal processing applications
    Quan, X
    Embabi, SHK
    Sanchez-Sinencio, E
    [J]. IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE - PROCEEDINGS, 1998, : 277 - 280