Reduction of on-resistance in 4H-SiC Multi-RESURF MOSFETs

被引：1

作者：

Noborio, Masato ^{[1
]}

Negoro, Yuki ^{[1
]}

Suda, Jun ^{[1
]}

Kimoto, Tsunenobu ^{[1
]}

机构：

[1] Kyoto Univ, Dept Elect Sci & Engn, Nishikyo Ku, Kyotodaigaku Katsura, Kyoto 6158510, Japan

来源：

SILICON CARBIDE AND RELATED MATERIALS 2005, PTS 1 AND 2 | 2006年 / 527-529卷

关键词：

power device; MOSFET; reduced surface field (RESURF); self-aligned process; device simulation;

D O I：

10.4028/www.scientific.net/MSF.527-529.1305

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

SiC lateral MOSFETs with multi-RESURF structures have been fabricated by a self-aligned process. The "multi-RESURF" means "double RESURF" and "buried-p RESURF" structures, which have the buried-p region at the top and at the middle of RESURF region, respectively. The increase of net RESURT dose and the decrease of channel length lead to the reduced on-resistance. -The "buried-p RESURF" MOSFETs have higher on-resistances than the "double RESURF" MOSFETs, due to the resistance of parasitic MET inside the RESURF region. The dose designing for double RESURF MOSFETs has been optimized by using device simulation. A double RESURF MOSFET exhibits a breakdown voltage of 750 V and an on-resistance of 52 m Omega cm(2).

引用

页码：1305 / +

页数：2

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