Low-power CMOS active resistor independent on the threshold voltage

被引：0

作者：

Popa, C ^{[1
]}

Manolescu, AM ^{[1
]}

Mitrea, O ^{[1
]}

Glesner, M ^{[1
]}

机构：

[1] Univ Politehn Bucharest, Bucharest, Romania

来源：

ICES 2002: 9TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-111, CONFERENCE PROCEEDINGS | 2002年

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a new linearity improvement technique for a CMOS active resistor. The method is based on the cancellation of the main odd-order nonlinear terms and bulk effect, using a parallel connection of two active resistors opposite excited, with different polarisation voltages. The resistor is designed to work for an extended range of the input voltages, and achieves an improvement in linearity about a magnitude order. The utilization area of this active resistor includes, but are not limited to active filters, switched capacitor circuits or medical applications. Its theoretical estimated performance, linearity error 0.35% for an input range of 500mV, was confirmed by SPICE simulations. The circuit draws a very small amount of current from a 3.3V voltage source, being suitable for low-power applications. The resistor was implemented in 0.35mu CMOS AMS technology and the layout area is about 60mum x 80mum.

引用

页码：57 / 60

页数：4

共 50 条

[21] Low-voltage low-power CMOS current conveyors [J].

Elwan, HO ;

Soliman, AM .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 1997, 44 (09) :828-835

[22] Low-power and low-voltage CMOS digital design [J].

CSEM Cent Suisse d'Electronique et, de Microtechnique SA, Neuchatel, Switzerland .

Microelectron Eng, 1-4 (179-208)

[23] Low-voltage, low-power CMOS delay element [J].

Seoul Natl Univ, Seoul, Korea, Republic of .

IEEE J Solid State Circuits, 7 (966-971)

[24] A low-voltage, low-power CMOS delay element [J].

Kim, G ;

Kim, MK ;

Chang, BS ;

Kim, W .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (07) :966-971

[25] A low-voltage, low-power CMOS phase shifter [J].

Ferri, G ;

De Laurentiis, P .

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2000, 28 (02) :187-191

[26] Design of CMOS filter with low-voltage and low-power [J].

Li, ST ;

Wu, J ;

He, YG .

ICEMI '97 - CONFERENCE PROCEEDINGS: THIRD INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, 1997, :447-450

[27] Low-voltage low-power CMOS full adder [J].

Radhakrishnan, D .

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2001, 148 (01) :19-24

[28] Low-voltage and low-power CMOS voltage-to-current converter [J].

Liu, WH ;

Liu, SI .

IEICE TRANSACTIONS ON ELECTRONICS, 2004, E87C (06) :1029-1032

[29] High speed, low-power CMOS voltage buffers [J].

Neag, M ;

McCarthy, O .

CAS'98 PROCEEDINGS - 1998 INTERNATIONAL SEMICONDUCTOR CONFERENCE, 21ST EDITION, VOLS 1 AND 2, 1998, :175-180

[30] Supply and threshold voltage scaling for low power CMOS [J].

Gonzalez, R ;

Gordon, BM ;

Horowitz, MA .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (08) :1210-1216

← 1 2 3 4 5 →