A CMOS miller hold capacitance sample-and-hold circuit to reduce charge sharing effect and clock feedthrough

A technique using Miller capacitance in the sample-and-hold (S/H) circuit is introduced in this paper to reduce the charge sharing effect (CSE) due to the parasitic capacitance and clock feedthrough from a sampling switch. A compact cascode amplifier is used in the Miller feedback circuit. A ten times reduction in CSE and clock feedthrough is achieved. The S/H capacitor is split into two parts, C-sh1 and C-sh2. One of these S/H capacitors effectively reduces the CSE while the other capacitor reduces clock feedthrough.