An algorithm for I/O partitioning targeting 3D circuits and its impact on 3D-Vias

In this paper we discuss the migration of a 2D netlist with pre-placed I/Os to 3D circuits. For that, we present an algorithm to perform the partitioning of the I/O pins into various tiers targeting at I/O balancing and 3D-Vias minimization. We formulate the netlist migration constrained with respect to the preservation of some original netlist properties. The I/O partitioning algorithm is based on the logic distance between I/Os. Since there is no literature on I/O partitioning for 3D circuits we compared our algorithm with two simplistic approaches that targeted balance and min-cut respectively. Experimental results show that our algorithm can reduce the number of 3D-Vias compared to both algorithms, while balance is kept close to optimal. Most importantly, we showed that performing I/O partitioning separately we can reduce the number of 3D-Vias even more than existing solutions in the literature for the netlist partitioning. Additionally, we studied the area impact of the 3D-Vias resulted from the three algorithms targeting two different technologies for 3D circuits. We observed that specially in the Bulk based technologies the 3D-Via penalty is huge, favoring our algorithm.