A high-speed, programmable, CSD coefficient fir filter

被引：52
|
作者：
Tang, ZW [1 ]
Zhang, J
Min, H
机构：
[1] Fudan Univ, ASIC, Shanghai 200433, Peoples R China
[2] Fudan Univ, Syst State Key Lab, Shanghai 200433, Peoples R China
来源：
IEEE TRANSACTIONS ON CONSUMER ELECTRONICS | 2002年 / 48卷 / 04期
关键词：
finite impulse response filter; application specific integrated circuit; canonic signed-digit encode; booth multiplier; wallace adder tree;
D O I：
10.1109/TCE.2003.1196409
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new high-speed, programmable FIR filter is presented, which is a multiplierless filter with CSD encoding coefficients. In this paper, we propose a new programmable CSD encoding structure to make CSD coefficients programmable. Compared with the conventional FIR structure with Booth multipliers, this coding structure improves the speed of filter and decreases the area. In the end of this paper, we design a 10-bits, 18-taps video luminance filter with the presented filter structure. The completed filter core occupies 6.8x6.8 mm(2) of silicon area in 0.6mum 2P2M CMOS technology, and its maximum work frequency is 100MHz.
引用
收藏
页码：834 / 837
页数：4
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