Delay Calibration Circuit for Delay Lines

被引：0
|
作者：
Pandita, Bupesh
机构：
来源：
2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2015年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A circuit for delay calibration of delay lines has been proposed. The proposed circuit is attractive for forwarded-clock links. Novel delay cell and a clock conditioning block reduce startup and false lock problems. The proposed wide-range calibration circuit has been realized in a 28nm CMOS process.
引用
收藏
页码：850 / 853
页数：4
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