Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits

被引:54
作者
Kshirsagar, R. V. [1 ]
Patrikar, R. M. [2 ]
机构
[1] Priyadarshini Coll Engn, Dept Elect Engn, Nagpur 440019, Maharashtra, India
[2] Visveswaraya Natl Inst Tech, Dept Elec & Comp Sci, Nagpur 440022, Maharashtra, India
关键词
D O I
10.1016/j.microrel.2009.08.001
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Due to the shrinking of feature size and significant reduction in noise margins, nanoscale circuits have become more susceptible to manufacturing defects, interference from radiation and noise-related transient faults. Many of these faults are not permanent in nature but their occurrence can result in malfunctioning of circuits, either due to complexity of digital circuits or due to interaction with software. A fault-tolerant scheme such as triple-modular redundancy (TMR) is being implemented increasingly in digital systems. One of the drawbacks of this scheme is that the reliability of the voter circuit is assumed to be very high, which may not be true. Most of the implementation of digital circuits is in the form of integrated circuit; so all the circuit elements are fabricated with same technology and hence reliability of all the components is usually same. In this paper we are presenting a novel fault-tolerant voter circuit which itself can tolerate a fault and give error free output by improving the overall system's reliability. (C) 2009 Elsevier Ltd. All rights reserved.
引用
收藏
页码:1573 / 1577
页数:5
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