Influence of External Gate Resistance on UIS Capability in Superjunction MOSFET

We investigated the UIS capability for superjunction MOSFETs with respect to the external gate resistance (R-g) and the charge imbalance (CIB) by experiments as well as device simulations. Measured UIS capability depends not only on the CIB but also on the R-g. Higher UIS capability was exhibited for small R-g than for large Rg as deviating the CIB to Q(n)<Q(p) while the difference by R-g was small for Q(n)=Q(p). The device simulations indicated that the device destruction by UIS is assumed to be related to the re-conduction of channel current (I-ch). When the R-g is small, I-ch turns off once while V-ds has not increased enough to generate impact ionization. This transient behavior is different from the one for large R-g. After that, I-ch re-conduction occurs due to the high electric field beneath the MOS gate for Q(n)=Q(p) but suppressed for Q(n)<Q(p). The graded doping for N-column which reduces phosphorus concentration near the surface helps to suppress the reconduction and improves the UIS capability for small R-g condition.