Influence of External Gate Resistance on UIS Capability in Superjunction MOSFET

被引:0
|
作者
Honda, Masaaki [1 ]
Yamaji, Mizue [1 ]
Arai, Daisuke [1 ]
Suzuki, Noriaki [1 ]
Asada, Takeshi [1 ]
Hirasawa, Wataru [1 ]
Yamaguchi, Takeshi [1 ]
Watanabe, Yuji [1 ]
机构
[1] Shindengen Elect Mfg Co Ltd, Elect Device Div, 10-13 Minami Cho, Hanno, Saitama, Japan
来源
2019 31ST INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD) | 2019年
关键词
superjunction MOSFET; UIS; external gate resistance;
D O I
10.1109/ispsd.2019.8757613
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We investigated the UIS capability for superjunction MOSFETs with respect to the external gate resistance (R-g) and the charge imbalance (CIB) by experiments as well as device simulations. Measured UIS capability depends not only on the CIB but also on the R-g. Higher UIS capability was exhibited for small R-g than for large Rg as deviating the CIB to Q(n)<Q(p) while the difference by R-g was small for Q(n)=Q(p). The device simulations indicated that the device destruction by UIS is assumed to be related to the re-conduction of channel current (I-ch). When the R-g is small, I-ch turns off once while V-ds has not increased enough to generate impact ionization. This transient behavior is different from the one for large R-g. After that, I-ch re-conduction occurs due to the high electric field beneath the MOS gate for Q(n)=Q(p) but suppressed for Q(n)<Q(p). The graded doping for N-column which reduces phosphorus concentration near the surface helps to suppress the reconduction and improves the UIS capability for small R-g condition.
引用
收藏
页码:335 / 338
页数:4
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