Efficient Design Techniques of Flash ADC for High Speed and Ultra Low Power Applications

被引:0
|
作者
Kamate, Sujata S. [1 ]
Rajani, H. P. [2 ]
Mallaraddi, Vidyavati [2 ]
机构
[1] Hirasugar Inst Technol, Dept Elect & Commun Engn, Nidasoshi, Karnataka, India
[2] KLEs Dr MSS CET, Dept Elect & Commun Engn, Belagavi, Karnataka, India
来源
关键词
D O I
10.21786/bbrc/13.13/20
中图分类号
Q81 [生物工程学(生物技术)]; Q93 [微生物学];
学科分类号
071005 ; 0836 ; 090102 ; 100705 ;
摘要
Analog to Digital converters are the essential components of todays digital world. As these convert real time signal into its equivalent digital code, must be designed efficiently. This paper presents design of 3-bit high speed and power efficient Flash Analog to Digital Converter. Flash type Analog to Digital Converter is designed and implemented with different inverter based comparators and based ROM encoder. A high speed ROM encoder is designed to convert thermometer code to its equivalent binary code. The proposed research compares various inverter based comparators such as Threshold Inverter, Quantizer comparator, Single Inverter Comparator, Single Inverter Comparator with the reference voltage and LTE comparators, designed using cadence design tools with 180nm technological library. The simulation results show that Single Inverter Comparator consumes less power 5.647uW among TIQ and R-TIQ comparators. Single Inverter comparator with reference voltage consumes less power however with more delay. Here Flash ADCs are designed with various inverter based comparators and ROM encoder. The results show that TIQ comparator based ADCs consume power of 298.9uW, whereas ADC designed with Single Inverter Comparator consumes 459.8uW power.
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页码:144 / 149
页数:6
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