Highly Dependable 3-D Stacked Multicore Processor System Module Fabricated Using Reconfigured Multichip-on-Wafer 3-D Integration Technology

被引:0
作者
Lee, K-W. [1 ,2 ]
Hashimoto, H. [1 ]
Onishi, M. [1 ,2 ]
Konno, S. [1 ]
Sato, Y. [1 ]
Nagai, C. [1 ]
Bea, J-C [1 ,2 ]
Murugesan, M. [1 ,2 ]
Fukushima, T. [1 ,2 ]
Tanaka, T. [3 ]
Koyanagi, M. [1 ,2 ]
机构
[1] Tohoku Univ, New Ind Creat Hatchery Ctr NICHe, Sendai, Miyagi 980, Japan
[2] Tohoku Univ, Global INTegrat Initiat GINTI, Sendai, Miyagi 980, Japan
[3] Tohoku Univ, Dept Biomed Engn, Sendai, Miyagi 980, Japan
来源
2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2014年
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中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
A highly dependable 3-D stacked multicore processor module composed of 4-layer stacked 3-D multicore processor chip and 2-layer stacked 3-D cache memory chip is implemented using reconfigured multichip-on-wafer 3-D integration and backside TSV technologies for the first time. Tier boundary scan, self-repair circuits, and BIST circuits in the 4-layer stacked 3-D multicore processor chip and the basic read/write functions of memory circuits in the 2-layer stacked 3-D cache memory chip are successfully evaluated. High-density TSVs and micro-joining characteristics in the 3-D stacked chip were evaluated by a non-destructive method using high resolution X-ray CT scanning tool.
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页数:4
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