Feasibility Study of Wafer-Level Backside Process for InP-Based ICs

被引：14

作者：

Tsutsumi, Takuya ^{[1
]}

Hamada, Hiroshi ^{[1
]}

Sano, Kimikazu ^{[1
]}

Ida, Minoru ^{[1
]}

Matsuzaki, Hideaki ^{[1
]}

机构：

[1] NTT Corp, NTT Device Technol Labs, Atsugi, Kanagawa 2430198, Japan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2019年 / 66卷 / 09期

关键词：

Backside fabrication process; backside metallization; ground bounce; InP substrate; substrate resonance; trough substrate via; wafer thinning; GROUND-BOUNCE NOISE;

D O I：

10.1109/TED.2019.2928849

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper reports wafer-level backside process technology, established with the intent to ensure stable operation of InP ICs in the submillimeter wavelength band, which generally suffer from ground bounce and substrate resonance. Our process consists of thinning a 3-in InP wafer, forming dense vias with interval cooling steps, backside metallization with single-level wiring and crack-free dicing. We investigate the effects of the backside process on InP-based heterojunction bipolar transistors and high electron mobility transistors. The results show that the backside process contributes to stable operation up to the 300-GHz range without any degradation of transistor characteristics.

引用

页码：3771 / 3776

页数：6

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