An Efficient Algorithm for Statistical Timing Yield Optimization

被引:3
作者
Ramprasath, S. [1 ]
Vasudevan, V. [1 ]
机构
[1] Indian Inst Technol, Dept Elect Engn, Madras 600036, Tamil Nadu, India
来源
2015 52ND ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC) | 2015年
关键词
Timing Yield; Yield Optimization; Gate sizing;
D O I
10.1145/2744769.2744796
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Statistical timing yield optimization algorithms require computation of yield-gradient for gate resizing in every iteration. Numerical yield-gradients account for the effects of fan-in and fan-out gates, but are computationally expensive. In this paper, we formulate a more accurate analytical expression for the yield-gradient (termed effective yield-gradient) that includes these effects. Based on the statistical properties of the path delay variations, we derive a simplified expression for the effective yield gradient that is accurate and results in an improvement in the run-time. Using these simplified expressions, we also propose an algorithm for resizing multiple gates in an iteration. Results on ITC99 and ISCAS85 benchmarks show that the proposed multi-node resizing algorithm results in 83% improvement in the run-time with an average area penalty of 3% and no cost to the final yield achieved.
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页数:6
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