PLL-Based Frequency Synthesizer Analysis and Simulation

Phase-locked loop (PLL) forms the basis of frequency synthesizers which have been widely used in radio communications. One of the main building blocks in a frequency synthesizer is the digital divider placed in the feedback path which determines the scaling factor of the synthesizer. In order to synthesize a high frequency output, a higher scaling factor is required and this also demands for a higher loop gain to maintain its performance. However, as the PLL is inherently nonlinear, the usual linear approximation method is not valid to guarantee the stability of the synthesizer in general. In this work, we present a nonlinear analysis of the frequency synthesizer which resembles a Lur'e system with a sector- and slope-bounded nonlinearity in z-domain. One of the absolute stability methods suitable for such a system, namely the Jury-Lee criterion, has been used to search for the maximum loop gain and the scaling factor for which the synthesizer remains locked. The optimization problem is formulated in terms of a linear matrix inequality (LMI) which is computationally more attractive than frequency-based conditions (This work was supported by Fundamental Research Grant Scheme (203/PELECT/6071267), Ministry of Education of Malaysia.).