A novel design of fault-tolerant RAM cell in quantum-dot cellular automata with physical verification

Quantum-dot cellular automata (QCA) emerged as a viable alternative to CMOS technology in nanotechnology. Despite the potential advantages of QCA compared with CMOS technology, QCA circuits often suffer from various manufacturing defects such as cell omission, cell displacement, and extra-cell deposition, which make them unreliable and fault-prone. Hence, it is essential in QCA technology to design a fault-tolerant circuit. The design of an optimized, high-speed RAM memory has received increasing attention of researchers as the memory unit is an essential component in the digital systems. In this paper, a new design of a fault-tolerant RAM cell is introduced using two proposed fault-tolerant three- and five-input majority gates. The proposed fault-tolerant majority gates have been evaluated in the presence of variety of defects such as cell omission, cell displacement and extra-cell deposition. The QCADesigner 2.0.3 and QCAPro tools are used for our simulations. The results indicate that the proposed majority gates have less energy consumption and more fault tolerance in comparison with the previous works. Furthermore, some physical calculations are presented to assess the functionality of the proposed gates.