All digital spread spectrum clock generator for EMI reduction

被引:39
作者
Damphousse, Simon [1 ]
Ouici, Khalid [1 ]
Rizki, Ahmed [1 ]
Mallinson, Martin [1 ]
机构
[1] ESS Technol Inc, Kelowna, BC V1Y 9R9, Canada
关键词
clock; CMOS; delay line; EMI reduction; spread spectrum; SSCG;
D O I
10.1109/JSSC.2006.886525
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An effective solution to control electromagnetic interference in computing appliances such as DVD players or home theater systems is to apply modulation on the system clock. The presence of modulation on the clock reduces the radiated power per unit bandwidth. We present the implementation-of a spread spectrum clock generator (SSCG) using strictly digital components. A digital delay line (DDLi) controlled by a small digital circuit is used to increase or decrease the delay on a clock and hence create a modulated output. The DDLi total electrical length is no longer than one period of the 27-MHz reference clock as the digital circuit can adjust to the limited length of the line. The circuit can produce up or down spread by modulating the frequency of the reference with a triangular waveform. The measured peak power reduction is greater than 13 dB for a deviation of about 3% and a frequency modulation of 100 kHz. A real-time digital calibration circuit enables a process and temperature independent operation. The circuit occupies 0.06 mm(2) in a 0.15-mu m CMOS process and consumes 7.1 mW.
引用
收藏
页码:145 / 150
页数:6
相关论文
共 5 条
[1]   A spread-spectrum clock generator with triangular modulation [J].
Chang, HH ;
Hua, IH ;
Liu, SI .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (04) :673-676
[2]  
Chen HW, 2001, IEICE T ELECTRON, VE84C, P1959
[3]  
Chen WT, 2005, IEEE INT SYMP CIRC S, P2643
[4]  
HARDIN KB, 1994, 1994 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY - COMPATIBILITY IN THE LOOP, P227, DOI 10.1109/ISEMC.1994.385656
[5]  
MICHEL JY, 1999, P IEEE INT ASIC SOC, P362