A new multi-objective mathematical model for the high-level synthesis of integrated circuits

被引:5
作者
Aras, Necati [1 ]
Yurdakul, Arda [2 ]
机构
[1] Bogazici Univ, Dept Ind Engn, Istanbul, Turkey
[2] Bogazici Univ, Dept Comp Engn, Istanbul, Turkey
关键词
Integrated circuits; Multiobjective optimization; Mixed-integer linear programming; Pareto frontier; ALLOCATION;
D O I
10.1016/j.apm.2015.09.061
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
An integrated circuit contains millions of components, all of which have to fit in the reserved silicon area and fulfill a defined functionality within a specified amount of execution time. Therefore, the design of an effective integrated circuit is a nontrivial task. Actually, it can be considered as a multi-objective optimization problem with two conflicting objectives: minimizing the total execution time called latency and the total silicon area of the integrated circuit. The overall problem is composed of tightly-coupled subproblems, i.e., determining the allocation of operators that execute the operations, the assignment of operations to operators, and scheduling of the operations. We formulate a multi-objective mixed-integer linear programming model (MOMILP) to solve this complex problem. It is novel since it incorporates decisions about the so-called multiplexers, which are essential components of an integrated circuit. The proposed MOMILP model is solved exactly using an augmented epsilon-constrained method. This enables us to find all the Pareto optimal solutions and hence the Pareto frontier for a given problem instance within a reasonable amount of computation time. The minimum latency and minimum area solutions of our model are 13.20 and 7.24% better on the average than the model that ignores multiplexers. (C) 2015 Elsevier Inc. All rights reserved.
引用
收藏
页码:2274 / 2290
页数:17
相关论文
共 33 条
[11]  
De Micheli G., 1994, SYNTHESIS OPTIMIZATI
[12]   Optimal Allocation of Surgery Blocks to Operating Rooms Under Uncertainty [J].
Denton, Brian T. ;
Miller, Andrew J. ;
Balasubramanian, Hari J. ;
Huschka, Todd R. .
OPERATIONS RESEARCH, 2010, 58 (04) :802-816
[13]  
Fazlali Mahmood, 2009, Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT 2009), P339, DOI 10.1109/FPT.2009.5377678
[14]  
Hadjis S, 2012, FPGA 12: PROCEEDINGS OF THE 2012 ACM-SIGDA INTERNATIONAL SYMPOSIUM ON FIELD PROGRAMMABLE GATE ARRAYS, P111
[15]  
Hara-Azumi Y, 2012, ASIA S PACIF DES AUT, P251, DOI 10.1109/ASPDAC.2012.6164954
[16]  
Herve N., 2007, P 3 INT C REC COMP A
[17]  
Huang C.-Y., 1990, P DES AUT C DAC 90
[18]   A Functional Unit and Register Binding Algorithm for Interconnect Reduction [J].
Kim, Taemin ;
Liu, Xun .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2010, 29 (04) :641-646
[19]  
Kondratyev A., 2011, IEEE DATE, P1
[20]  
Krishnan V, 2007, VLSI-SOC 2007: PROCEEDINGS OF THE 2007 IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION, P99