A High-Speed FPGA Implementation of AES for Large Scale Embedded Systems and its Applications

In this paper, a high-speed hardware implementation of the AES encryption algorithm is presented. targeting the large scale and high bandwidth embedded systems and applications. The high-speed implementation is developed by employing the pipelining architectural technique, where the fully sub pipelined architecture is applied efficiently. The applied architecture is performed using the AES 128-bit data path. The fully sub pipelined architectural technique is implemented by constructing the S-boxes of the AES encryption algorithm using the BRAMs of the FPGA device. The pipelined design is realized on the new Xilinx FPGA devices, Artix-7, Virtex-7, Kintex-7, Spartan-7, and Kintex UltraScale. The proposed design is fully synthesized, translated, placed, and routed using the new Xilinx Vivado 2020 design suite. The hardware implementation results of the proposed pipelined design show an efficiency in terms of speed, utilized resources, and throughput. Comparing with previous works, our proposed pipelined design utilizes less FPGA resources, operates at high operating frequencies, and delivers high throughputs.