100 Gbit/s multiplexing and demultiplexing IC operations in InPHEMT technology

被引:5
作者
Murata, K [1 ]
Sano, K [1 ]
Sugitani, S [1 ]
Sugahara, H [1 ]
Enoki, T [1 ]
机构
[1] NTT Corp, NTT Photo Labs, Atsugi, Kanagawa 2430198, Japan
关键词
Demultiplexing - Flip flop circuits - High electron mobility transistors - Microelectronics - Multiplexing - Semiconducting indium phosphide;
D O I
10.1049/el:20021067
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The 100 Gbit/s multiplexing operation of a selector IC and the demultiplexing operation of a D-type flip-flop (D-FF) using a production-level 0.1 mum-gate InP HEMT IC technology is described. Eye-openings of the selector IC at 100 Gbit/s and its error-free operation were confirmed using a test chip containing the selector and the D-FF To the authors' best knowledge, this is the first report of 100 Gbit/s operation of a transistor-based integrated circuit.
引用
收藏
页码:1529 / 1531
页数:3
相关论文
共 8 条
[1]  
ENOKI T, 1995, INT C IND PHOSPH REL, P81
[2]   Very-high-speed selector IC using InP/InGaAs heterojunction bipolar transistors [J].
Ishii, K ;
Murata, K ;
Ida, M ;
Kurishima, K ;
Enoki, T ;
Shibata, T ;
Sano, E .
ELECTRONICS LETTERS, 2002, 38 (10) :480-481
[3]  
*ITUT, 2001, G709 ITUT
[4]  
Murata K, 2000, IEICE T ELECTRON, VE83C, P1166
[5]   An 80-Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMT's [J].
Otsuji, T ;
Murata, K ;
Enoki, T ;
Umeda, Y .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (09) :1321-1327
[6]  
RODWELL M, 2001, SEL TOP ELECT SYST, V21
[7]  
Sano K, 2000, IEICE T ELECTRON, VE83C, P1786
[8]  
Suzuki T., 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), P192, DOI 10.1109/ISSCC.2002.993001