A scalable system architecture for high-throughput turbo-decoders

被引：16

作者：

Thul, MJ ^{[1
]}

Gilbert, F ^{[1
]}

Vogt, T ^{[1
]}

Kreiselmaier, G ^{[1
]}

Wehn, N ^{[1
]}

机构：

[1] Univ Kaiserslautern, Microelect Syst Design Res Grp, D-67663 Kaiserslautern, Germany

来源：

JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY | 2005年 / 39卷 / 1-2期

关键词：

Turbo-Decoder; high-throughput; wireless; parallel decoding; interleaving; VLSI architectures;

D O I：

10.1023/B:VLSI.0000047272.75049.0e

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The need for higher data rates is ever rising as wireless communications standards move from the third to the fourth generation. Turbo-Codes are the prevalent channel codes for wireless systems due to their excellent forward error correction capability. So far research has mainly focused on components of high throughput Turbo-Decoders. In this paper we explore the Turbo-Decoder design space anew, both under system design and deep-submicron implementation aspects. Our approach incorporates all levels of design, from I/O behavior down to floorplaning taking deep-submicron effects into account. Its scalability allows to derive optimized architectures tailored to the given throughput and target technology. We present results for 3GPP compliant Turbo-Decoders beyond 100 Mbit/s synthesized on a 0.18 mum standard cell library.

引用

页码：63 / 77

页数：15

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