A 2D model for radiation-hard CMOS annular transistors

被引：3

作者：

Lopez, P. ^{[1
]}

Blanco-Filgueira, B. ^{[1
]}

Pardo, F. ^{[2
]}

Cabello, D. ^{[1
]}

Hauer, J. ^{[3
]}

机构：

[1] Univ Santiago de Compostela, Dept Elect & Comp Sci, Santiago De Compostela 15782, Spain

[2] Univ Valladolid, Dept Elect Technol, Valladolid 47014, Spain

[3] Fraunhofer Inst Integrated Circuits, D-91058 Erlangen, Germany

来源：

SEMICONDUCTOR SCIENCE AND TECHNOLOGY | 2009年 / 24卷 / 12期

关键词：

N-CHANNEL MOSFETS;

D O I：

10.1088/0268-1242/24/12/125009

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Scaling benefits of CMOS processes include the reduction of the oxide thickness, which in turn favors the reduction of threshold voltage shifts due to radiation-induced gate oxide trapped charge. Moreover, experimental results have shown that this inherent radiation hardness of deep submicron processes can be further exploited using gate-enclosed layout transistors with an annular design. For an in-depth analysis of such structures, we present in this paper a 2D analytical I-V model for short-channel annular devices based on the direct solution of the Poisson equation in cylindrical coordinates. The theoretical approach is confirmed with experimental data in a standard CMOS 0.18 mu m process.

引用

页数：6