Design of Heterogeneous Reconfigurable Cipher Engine basing on FPGA plus ASIC

With the demand for Big Data cryptographic computation and the rapid development of Very Large Scale Integration (VLSI), many specific cipher chips emerge prominently to accelerate the process of cipher algorithm execution. Meanwhile reconfigurable computing technology is more and more applied to the design of cipher chips. This paper concludes and analyses the relative merits of the hardware architectures of different reconfigurable cipher chips, and proposes a novel heterogeneous hardware architecture of reconfigurable cipher engine - RCHA. This architecture combines the merits of FPGA and ASIC, which can not only flexibly realize a number of cipher algorithms, but also improves the performance of cipher chips.