Improved SPICE Macromodel of Phase Change Random Access Memory

被引:5
作者
Chang, Huan-Lin [1 ,2 ]
Chang, Hung-Chih [1 ,2 ]
Yang, Shang-Chi [1 ,2 ]
Tsai, Hsi-Chun [1 ,2 ]
Li, Hsuan-Chih [1 ,2 ]
Liu, C. W. [1 ,2 ]
机构
[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan
[2] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan
来源
2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM | 2009年
关键词
HSPICE MACROMODEL; MODEL;
D O I
10.1109/VDAT.2009.5158113
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents an improved SPICE macromodel of phase change random access memory (PCRAM). Based on the circuit-based model architecture in [1], the novelty of this work lies in (1) accurate modeling the current-voltage (I-P) plot including the snap-back phenomenon, and (2) solution to the falling edge problem to avoid misrepresentation of the PCRAM state, and (3) calibration of the crystallization time for potential multilevel (ML) operation of the PCRAM.
引用
收藏
页码:134 / +
页数:2
相关论文
共 6 条
[1]   Parameterized SPICE model for a phase-change RAM device [J].
Cobley, RA ;
Wright, CD .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (01) :112-118
[2]   A compact HSPICE macromodel of resistive RAM [J].
Lee, Jin-Gu ;
Kim, Dae Hwan ;
Lee, Jae Gab ;
Kim, Dong Myong ;
Min, Kyeong-Sik .
IEICE ELECTRONICS EXPRESS, 2007, 4 (19) :600-605
[3]  
Liao YB, 2007, BMAS 2007: PROCEEDINGS OF THE 2007 IEEE INTERNATIONAL BEHAVIORAL MODELING AND SIMULATION WORKSHOP, P159
[4]   Comprehensive numerical model for phase-change memory simulations [J].
Redaelli, A ;
Lacaita, AL ;
Benvenuti, A ;
Pirovano, A .
SISPAD: 2005 International Conference on Simulation of Semiconductor Processes and Devices, 2005, :279-282
[5]   A phase change memory compact model for multilevel applications [J].
Ventrice, D. ;
Fantini, P. ;
Redaelli, Andrea ;
Pirovano, A. ;
Benvenuti, A. ;
Pellizzer, F. .
IEEE ELECTRON DEVICE LETTERS, 2007, 28 (11) :973-975
[6]   HSPICE macromodel of PCRAM for binary and multilevel storage [J].
Wei, XQ ;
Shi, LP ;
Walia, R ;
Chong, TC ;
Zhao, R ;
Miao, XS ;
Quek, BS .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (01) :56-62