Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions

被引：31

作者：

Wu, Jun ^{[1
]}

Babadi, Aein Shiri ^{[1
]}

Jacobsson, Daniel ^{[2
]}

Colvin, Jovana ^{[3
]}

Yngman, Sofie ^{[3
]}

Timm, Rainer ^{[3
]}

Lind, Erik ^{[1
]}

Wemersson, Lars-Erik ^{[1
]}

机构：

[1] Lund Univ, Elect & Informat Technol, POB 118, SE-22100 Lund, Sweden

[2] Lund Univ, Solid State Phys, POB 118, SE-22100 Lund, Sweden

[3] Lund Univ, Synchrotron Radiat Res, POB 118, SE-22100 Lund, Sweden

来源：

NANO LETTERS | 2016年 / 16卷 / 04期

基金：

瑞典研究理事会;

关键词：

Nanowire; C-V; D-it; growth; doping; crystalline phase; ATOMIC-SCALE STRUCTURE; ZINC BLENDE; INAS NANOWIRES; CAPACITORS; WURTZITE; SURFACES; MOSFETS; SILICON; SI; TRANSISTORS;

D O I：

10.1021/acs.nanolett.5b05253

中图分类号：

O6 [化学];

学科分类号：

0703 ;

摘要：

In this paper, we correlate the growth of InAs nanowires with the detailed interface trap density (D-it) profile of the vertical wrap-gated InAs/high-k nanowire semiconductor-dielectric gate stack. We also perform the first detailed characterization and optimization of the influence of the in situ doping supplied during the nanowire epitaxial growth on the sequential transistor gate stack quality. Results show that the intrinsic nanowire channels have a significant reduction in D-it as compared to planar references. It is also found that introducing tetraethyltin (TESn) doping during nanowire growth severely degrades the D-it profile. By adopting a high temperature, low V/III ratio tailored growth scheme, the influence of doping is minimized. Finally, characterization using a unique frequency behavior of the nanowire capacitance-voltage (C-V) characteristics reveals a change of the dopant incorporation mechanism as the growth condition is changed.

引用

页码：2418 / 2425

页数：8

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