Low power sampling latch for up to 25 Gb/s 2x oversampling CDR in 90-nm CMOS

被引：0

作者：

von Bueren, G. ^{[1
]}

Rodoni, L. ^{[1
]}

Kromer, C. ^{[1
]}

Jaeckel, H. ^{[1
]}

Huber, A. ^{[2
]}

T., Morf ^{[3
]}

机构：

[1] ETH, Swiss Fed Inst Technol, Elect Lab, CH-8092 Zurich, Switzerland

[2] Fachhochschule Nordwestschweiz, IME, CH-5210 Windisch, Switzerland

[3] IBM Corp, Zurich Res Lab, CH-8803 Ruschlikon, Switzerland

来源：

ESSCIRC 2006: PROCEEDINGS OF THE 32ND EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2006年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A sampling latch for full-, half and quarter-rate clock and data recovery circuits at data rates of 12.5 Gb/s, 20 Gb/s and 25 Gb/s, respectively, achieving a bit error rate lower than 10(-12) is presented. The circuit is implemented in a 90-nm CMOS technology. The master-slave D-FF including peaking inductors consumes only 1 mW of power and requires a small area of 30x20 mu m(2).

引用

页码：106 / +

页数：2

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