Design and implementation of MPEG-2/DVB scrambler unit and VLSI chip

被引:8
作者
Kim, WH
Chen, KJ
Cho, HS
机构
[1] Satellite Communication Division, ETRI, Taejon
关键词
D O I
10.1109/30.628778
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper describes the MPEG-2/DVB Scrambler Unit(DVB-SU) and VLSI chip developed for the ETRI's Conditional Access System(CAS) of Digital Broadcasting System. The DVB-SU is designed and implemented based on an ASIC, FPGAs and a DSP. The ASIC, compliant with EP-DVB common scrambling specification, is 128-pin MQFP type and operated in 50 MHz system clock. It has features of flexible conditional access handling and interface with commercial MPEG-2 multiplexer in compliance with MPEG-2 system spec.(ISO/IEC 13818). It had been integrated as a part of Conditional Access Sub-system of digital broadcasting system and conformed that it met all initial objectives and performance requirements.
引用
收藏
页码:980 / 985
页数:6
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