A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8V, 0.18 μm CMOS technology

被引：13

作者：

Kuo, H ^{[1
]}

Verbauwhede, I ^{[1
]}

Schaumont, P ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Elect Engn Dept, Los Angeles, CA 90024 USA

来源：

PROCEEDINGS OF THE IEEE 2002 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2002年

关键词：

D O I：

10.1109/CICC.2002.1012785

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In October 2000 the National Institute of Standard and Technology (NIST) chose the Rijndael algorithm as the new Advanced Encryption Standard (AES). In this paper we present an ASIC implementation of the Rijndael core. The core includes a non-pipelined encryption datapath with an on-the-fly key schedule data path. At a nominal 1.8V, the IC runs at 125 MHz resulting in a throughput of 2.29 Gbits/sec while consuming 56 mW. At 1.95V, the chip can operate up to 154 MHz with an equivalent throughput of 2.8 Gbits/sec and consumes 82 mW.

引用

页码：147 / 150

页数：4