An ultra low voltage SOI CMOS pass-gate logic

被引：0

作者：

Fuse, T ^{[1
]}

Oowaki, Y ^{[1
]}

Terauchi, M ^{[1
]}

Watanabe, S ^{[1
]}

Yoshimi, M ^{[1
]}

Ohuchi, K ^{[1
]}

Matsunaga, J ^{[1
]}

机构：

[1] TOSHIBA CO LTD, MICROELECT ENGN LAB, KAWASAKI, KANAGAWA 210, JAPAN

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 1997年 / E80C卷 / 03期

关键词：

SOI; 0.5 V operation; ultra low voltage; pass-gate logic; body bias control;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An ultra low voltage CMOS pass-gate logic using body-bias controlled SOI MOSFETs has been developed. The logic is composed of gate-body connected SOI pass-gates and a CMOS buffer with the body-bias controlled by the complementary double-rail input. The full-adder using the proposed logic improved the lowest operation voltage by 27%, compared with the SOI CPL (Complementary Pass-Gate Logic). For a 16 X 16 bit multiplier, the power-delay product achieved 70 pJ (including 50 pF I/O) at 0.5 V power supply, which was more than 1 order of magnitude improvement over the bulk CPL.

引用

页码：472 / 477

页数：6

共 50 条

[31] A Digital-Based Ultra-Low-Voltage Pseudo-Differential CMOS Schmitt Trigger
Bastan, Yasin
Amiri, Parviz
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2020, 29 (04)
[32] Ultra Low-Voltage Rail-to-Rail Comparator Design in 130 nm CMOS Technology
Nagy, Lukas
Arbet, Daniel
Kovac, Martin
Potocny, Miroslav
Stopjakova, Viera
2019 IEEE 22ND INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS), 2019,
[33] Novel High-Speed Dynamic Differential Ultra Low Voltage Logic for supply-voltage below 300 mV
Mirmotahari, O.
Dadashi, A.
Azadmehr, M.
Berg, Y.
2015 IEEE CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (ICECS), 2015, : 53 - 56
[34] Implementation of Boolean Logic Functions Through Double Gate FD-SOI MOSFET
Ansari, Md. Hasan Raza
El-Atab, Nazek
IEEE ACCESS, 2024, 12 : 128810 - 128815
[35] A novel ultra low-voltage/low-power rail-to-rail comparator topology in nanoscale CMOS technology
Nagy, Lukas
Potocny, Miroslav
Ondica, Robert
Hudec, Adam
Stopjakova, Viera
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2023, 166
[36] Gate Leakage Current Effects on the Linearity of 28GHz CMOS SOI Power Amplifiers
Rabet, Bagher
Rostomyan, Narek
Asbeck, Peter
2019 IEEE TOPICAL CONFERENCE ON RF/MICROWAVE POWER AMPLIFIERS FOR RADIO AND WIRELESS APPLICATIONS (PAWR), 2019, : 235 - 238
[37] IMPACT OF TEMPERATURE ON THRESHOLD VOLTAGE & SELF HEATING IN ULTRA THIN SOI MOSFET
Mani, Prashant
Pandey, Manoj Kumar
2019 6TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN), 2019, : 796 - 798
[38] Influence of Threshold Voltage Performance Analysis on Dual Halo Gate Stacked Triple Material Dual Gate TFET for Ultra Low Power Applications
Venkatesh, M.
Balamurugan, N. B.
SILICON, 2021, 13 (01) : 275 - 287
[39] A Low Noise Amplifier in 130 nm SOI CMOS for ISM Applications
Han, Jiang-An
Kong, Zhi-Hui
Yu, Bo
Yang, Wan-Lan
Ma, Kaixue
Yeo, Kiat Seng
2015 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2015, : 203 - 204
[40] An overview of low-frequency noise in advanced CMOS/SOI transistors
Jomaah, J
Balestra, F
NOISE IN DEVICES AND CIRCUITS, 2003, 5113 : 159 - 167

← 1 2 3 4 5 →