A fast and accurate delay dependent method for switching estimation of large combinational circuits

被引：2

作者：

Theoharis, S

Theodoridis, G

Soudris, D ^{[1
]}

Goutis, C

Thanailakis, A

机构：

[1] Democritus Univ Thrace, Dept Elect & Comp Engn, VLSI Design & Testing Ctr, GR-67100 Xanthi, Greece

[2] Univ Patras, Dept Elect & Comp Engn, VLSI Design & Testing Ctr, Rion 26110, Greece

[3] ALMA Technol, Pikermi Attika 19009, Greece

来源：

JOURNAL OF SYSTEMS ARCHITECTURE | 2002年 / 48卷 / 4-5期

关键词：

gate level; power estimation; CMOS circuit; low power design; computer aided design;

D O I：

10.1016/S1383-7621(02)00120-0

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Assuming inertial gate delay model, the first-order temporal correlation and the structural dependencies, a probabilistic method to estimate the switching activity of a combinational circuit, is introduced. To capture the first temporal correlation a novel mathematical model and the associated new formulas are derived. Also, a modified boolean function, which describes the logic and timing behavior of each signal, is introduced. To capture the structural dependencies an efficient new method to partition a large circuit into small independent sub-circuits is proposed. Finally, an algorithm that evaluates the switching activity of any circuit node is presented. (C) 2002 Elsevier Science B.V. All rights reserved.

引用

页码：113 / 124

页数：12

共 50 条

[31] A method of generating tests with linearity property for gate delay faults in combinational circuits
Takahashi, H
Boateng, KO
Takamatsu, Y
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 1999, E82D (11): : 1466 - 1473
[32] A fast and accurate power estimation methodology for QDI asynchronous circuits
Ghavami, Behnam
Niknahad, Mahtab
Najibi, Mehrdad
Pedram, Hossein
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2007, 4644 : 463 - +
[33] A Combinational Logic Optimization Method for Large-Scale SFQ Circuits
Lin, Qun
Yang, Shucheng
Weng, Bicong
Ren, Jie
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2024, 34 (09)
[34] A Fast and Accurate Reliability Simulation Method for Analog Circuits
Toro-Frias, A.
Castro-Lopez, R.
Roca, E.
Fernandez, F. V.
Martin-Martinez, J.
Rodriguez, R.
Nafria, M.
2015 INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD), 2015,
[35] Design-for-testability for path delay faults in large combinational circuits using test points
Pomeranz, I
Reddy, SM
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1998, 17 (04) : 333 - 343
[36] Design-for-testability for path delay faults in large combinational circuits using test points
Univ of Iowa, Iowa City, United States
IEEE Trans Comput Aided Des Integr Circuits Syst, 4 (333-343):
[37] Delay time estimation model for large digital CMOS circuits
Kim, DW
Choi, TY
VLSI DESIGN, 2000, 11 (02) : 161 - 173
[38] Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits
Liu, Jiantao
Graczyk, Maksymilian
Guerrieri, Andrea
Josipovic, Lana
2024 34TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, FPL 2024, 2024, : 118 - 125
[39] An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuits
Zhang, K
Takase, H
Hayashi, T
Kita, H
PROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997, 1996, : 107 - 112
[40] AN EFFICIENT NONENUMERATIVE METHOD TO ESTIMATE THE PATH DELAY-FAULT COVERAGE IN COMBINATIONAL-CIRCUITS
POMERANZ, I
REDDY, SM
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1994, 13 (02) : 240 - 250

← 1 2 3 4 5 →