A High-Speed Digital Signal Hierarchical Parallel Processing Architecture Based on CPU-GPU Platform

被引：0
|
作者：
Yan Di [1 ]
Shuai Weiyi [1 ]
Sun Ke [2 ]
Li Zibo [3 ]
机构：
[1] Equipment Acad, Beijing, Peoples R China
[2] Beijing Aerosp Control Ctr, Beijing, Peoples R China
[3] China Xian Satellite Control Ctr, Xian, Shaanxi, Peoples R China
来源：
2017 17TH IEEE INTERNATIONAL CONFERENCE ON COMMUNICATION TECHNOLOGY (ICCT 2017) | 2017年
关键词：
CPU-GPU platform; HPPA; real-time; latency; throughput rate; block processing;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Digital signal processing on the CPU-GPU platform has advantages of flexibility, scalability and easy maintenance. The powerful parallel processing capability of the CPU-GPU platform makes it inherently advantageous in high-speed signal processing. A hierarchical parallel processing architecture (HPPA) is proposed. This architecture uses a block processing technique different from stream processing used by field programmable gate array (FPGA). The main components are designed and the real-time performance of the architecture is analyzed. Conclusions can be used to determine the number of processing branches to ensure the real-time performance of the system.
引用
收藏
页码：355 / 358
页数：4
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