Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors

被引：10

作者：

Klosowski, Miron ^{[1
]}

Sun, Yichuang ^{[2
]}

机构：

[1] Gdansk Univ Technol, Fac Elect Telecommun & Informat, 11-12 Gabriela Narutowicza St, PL-80233 Gdansk, Poland

[2] Univ Hertfordshire, Sch Engn & Comp Sci, Hatfield AL10 9AB, Herts, England

来源：

SENSORS | 2020年 / 20卷 / 20期

关键词：

image sensor; fixed pattern noise; gain correction; offset correction; integral nonlinearity correction; time-mode ADC; ARRAY; OPTIMIZATION; ARCHITECTURE; DESIGN; ADC;

D O I：

10.3390/s20205921

中图分类号：

O65 [分析化学];

学科分类号：

070302 ; 081704 ;

摘要：

In the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated using 128-pixel CMOS imager. The reduction of the PRNU to about 0.5 LSB has been achieved. Linearity improvement technique has also been proposed, which allows for integral nonlinearity (INL) reduction to about 0.5 LSB. Measurements confirm the proposed approach.

引用

页码：1 / 16

页数：16

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