Reduction of power consumption of RSFQ circuits by inductance-load biasing

We propose an inductance-load-biasing method in order to reduce power consumption of rapid single flux quantum (SFQ) logic circuits. The main idea arises from the fact that a current source can be made of a large inductor accompanied by a large flux. In our proposal, the current source is composed of a large inductor L-b, a Small resistor R-b and a small voltage source V-b. Computer simulations of inductance-load-biased Josephson transmission lines (JTLs) show that an SFQ pulse propagates correctly when L-b is large enough even if R-b is very small. In order to implement the inductance-load-biased JTL, we have made two different layouts: one uses a large bias inductance L-b of a typical stripline structure on a ground plane which occupies a rather large area; the other uses L-b in the shape of a coplanar stripline, which costs a smaller area.